Dr Shane Fleming

Honorary Lecturer

Computer Science

+44 (0) 1792 987383

s.t.fleming@swansea.ac.uk

Post Graduate / RA Project Area - 208
Second Floor
Computational Foundry
Bay Campus

About

Dr Shane Fleming is a Lecturer in the Department of Computer Science. His research is in the area of custom digital hardware. In particular, he is interested in investigating how better tools and abstractions can make the construction of custom hardware easier, safer, and more efficient.

He primarily works with FPGA devices with applications ranging from low-powered embedded systems, such as satellite systems, to high-performance datacentres.

Publications

Research Highlights

Fleming, S. & Thomas, D. (2017). Using Runahead Execution to Hide Memory Latency in High Level Synthesis. In 2017 IEEE 25th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM)IEEE.
https://doi.org/10.1109/fccm.2017.33, SU Repository: https://cronfa.swan.ac.uk/Record/cronfa57993
Fleming, S. & Thomas, D. (2019). Injecting FPGA Configuration Faults in Parallel. In 2018 International Conference on Field-Programmable Technology (FPT)IEEE.
https://doi.org/10.1109/fpt.2018.00037, SU Repository: https://cronfa.swan.ac.uk/Record/cronfa57991
Naylor, M., Moore, S., Thomas, D., Beaumont, J., Fleming, S., Vousden, M., Markettos, A., Bytheway, T., & Brown, A. (2021). General hardware multicasting for fine-grained message-passing architectures. In 2021 29th Euromicro International Conference on Parallel, Distributed and Network-Based Processing (PDP) (pp. 126-133). IEEE.
https://doi.org/10.1109/pdp52278.2021.00028, SU Repository: https://cronfa.swan.ac.uk/Record/cronfa56452
Cheng, J., Fleming, S., Chen, Y., Anderson, J., Wickerson, J., & Constantinides, G. (2022). Efficient Memory Arbitration in High-Level Synthesis From Multi-Threaded Code. IEEE Transactions on Computers, 71(4), 933-946.
https://doi.org/10.1109/tc.2021.3066466, SU Repository: https://cronfa.swan.ac.uk/Record/cronfa56451

All Research

Journal Articles

Cheng, J., Fleming, S., Chen, Y., Anderson, J., Wickerson, J., & Constantinides, G. (2022). Efficient Memory Arbitration in High-Level Synthesis From Multi-Threaded Code. IEEE Transactions on Computers, 71(4), 933-946.
https://doi.org/10.1109/tc.2021.3066466, SU Repository: https://cronfa.swan.ac.uk/Record/cronfa56451

Conference Contributions

Naylor, M., Moore, S., Thomas, D., Beaumont, J., Fleming, S., Vousden, M., Markettos, A., Bytheway, T., & Brown, A. (2021). General hardware multicasting for fine-grained message-passing architectures. In 2021 29th Euromicro International Conference on Parallel, Distributed and Network-Based Processing (PDP) (pp. 126-133). IEEE.
https://doi.org/10.1109/pdp52278.2021.00028, SU Repository: https://cronfa.swan.ac.uk/Record/cronfa56452
Fleming, S. & Thomas, D. (2019). Injecting FPGA Configuration Faults in Parallel. In 2018 International Conference on Field-Programmable Technology (FPT)IEEE.
https://doi.org/10.1109/fpt.2018.00037, SU Repository: https://cronfa.swan.ac.uk/Record/cronfa57991
Fleming, S. & Thomas, D. (2017). Using Runahead Execution to Hide Memory Latency in High Level Synthesis. In 2017 IEEE 25th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM)IEEE.
https://doi.org/10.1109/fccm.2017.33, SU Repository: https://cronfa.swan.ac.uk/Record/cronfa57993